1. Technical Field
The present disclosure relates to a semiconductor device and a semiconductor device package, and more particularly to a semiconductor device with metal bump structures and a package having the same.
2. Description of the Related Art
In a semiconductor device package, a semiconductor chip (also referred to as an integrated circuit (IC) chip or die) may be bonded directly to a packaging substrate. Such semiconductor chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is “flipped” onto its front surface (e.g., active circuit surface) so that the solder balls form electrical connections directly between the semiconductor chip and conductive metal pads, pre-solder, or traces on a packaging substrate. Packages of this type are commonly called “flip chip packages.”
As advances in semiconductor technology further increase the speed of semiconductor chips, a shift towards using a silicon based (Si) die with a plurality of layers of low dielectric constant (low-K) material have been sought. Low-K material assists in the reduction of propagation delay because of the lower dielectric constant, thereby improving the electrical performance of a low-K Si die. However, such low-K material is usually very brittle and has presented significant packaging problems (e.g., such as may affect reliability of the semiconductor chips).
In a conventional technique for a flip chip package, a die and a packaging substrate are electrically connected and mechanically bonded in a solder joining operation. Heat is applied, causing the solder bumps to alloy and form electrical connections between the die and the packaging substrate. The package is then cooled to harden the connection.
An underfill may then be applied in order to enhance the mechanical bonding of the die and substrate. An underfill material, typically a thermo-set epoxy, is dispensed into the space (or “gap”) between the die and the substrate. The underfill is then cured by heating.
Semiconductor packages are typically subject to temperature cycling during normal operation. A problem with flip chip package constructions as described above is that during the cool down from the solder joining temperature and the underfill curing, the whole package is highly stressed due to the different coefficients of thermal expansion (CTEs) of the substrate and die materials. Shrinkage of the substrate, typically an organic material having a relatively high CTE, is greater than shrinkage of the die, which typically is silicon-based and has a much lower CTE. The high stress experienced by these bonded materials during cooling may cause them to warp or crack and cause the package structure to bow. Consequently, the bow of the package may exceed a co-planarity specification for flip chip packages.
With the introduction of low-K Si dice and extra-low-K Si dice in flip chip packages, the problems experienced by conventional flip chip packages are of even greater significance. This is because, as compared to traditional dielectric materials in conventional silicon based dice, low-K dielectric materials are brittle, and tend to crack under substantially less mechanical or thermal stress. As such, it is possible for the reliability of the low-K Si die to be compromised due to cracking of the low-K dielectric material. In addition, the mismatches in thermal expansion between the low-k dielectric material, silicon based die, and substrate can lead to delamination or collapse of the low-K material in the packaged low-K Si die during its manufacture or during its use in the field. Low-K Si die's susceptibility to cracking, delaminating, or collapsing of the low-K material is generally applicable to all sizes of dice. Consequently, lower yield, poorer reliability, and higher costs may occur in the manufacturing and use of both the low-K Si dice themselves as well as the overall low-K Si die flip chip packages.
Accordingly, what is needed are low-K Si die flip chip packages that control package warpage within acceptable limits for incorporation into electronic devices, and that redistribute the package's internal stresses in enhancing both the low-K Si die and the low-K Si die flip chip package reliabilities.